The present invention relates to a noise reduction/elimination apparatus particularly for use with a rotary head type recording/reproducing apparatus. More particularly, the present invention relates to a noise reduction apparatus for use with a magnetic reproducing apparatus which picks up an FM modulated audio signal on a medium by means of a rotary head, and FM demodulates the picked-up audio signal to obtain the original audio signal, the noise reduction apparatus being capable of eliminating noises (hereinafter called jitter noises) generated by jitter from the picked-up audio signal.
Recently, recording/reproducing apparatuses have been practically used which records/reproduces video and audio information by a helical scanning scheme using a rotary head.
With the recording/reproducing apparatus of this type, in recording an audio signal, for example, a carrier wave is FM modulated by the audio signal and recorded on a recording medium such as a magnetic tape. In reproducing the original audio signal, the recorded signal is picked up from the recording medium and FM demodulated to obtain the original audio signal.
If the rotation locus of the tip of a magnetic head is a circle having a perfect roundness, the same FM modulated audio signal can be recorded and picked up even by using two different recording/reproducing apparatuses.
However, if the rotation locus of the tip of a magnetic head is not a perfect circle, frequency fluctuation is produced in both recorded and picked-up signals. Such a case will be described with reference to FIG. 1.
In FIG. 1, magnetic heads Ha and Hb are symmetrically mounted on a rotary head cylinder (hereinafter called simply a rotary cylinder) S with respect to the center O of the rotary cylinder. The rotary cylinder S rotates in the X arrow direction about its rotation center O', while a magnetic tape T runs herically in the Y arrow direction in contact with the outer periphery of the rotary cylinder S. It is assumed that the rotation center O' is eccentric by .DELTA.x from the center O. The fluctuation ratio .DELTA.v of a relative velocity of the magnetic head Ha is given by the following equation: EQU .DELTA.v=(r-.DELTA.x)/r (1)
where r represents the radius of the rotary cylinder S.
The frequency shift .DELTA.f of a recorded signal caused by the relative velocity fluctuation is given by the following equation: EQU .DELTA.f=fO/.DELTA.v-fO (2)
Since the two magnetic heads Ha and Hb mounted on the rotary cylinder S are alternately switched between consecutive recording tracks, the actual frequency shift amount becomes 2.DELTA.f. Assuming that the radius of the rotary head S is r=31 mm and the eccentric displacement is .DELTA.x=5 .mu.m, then it becomes .DELTA.v=0.9998387. If the frequency of a recorded signal is fO=1.7 MHz, the frequency shift amount becomes .DELTA.f=274 Hz so that the recorded signal is always subject to the frequency shift 2.DELTA.f=548 Hz.
Assuming that the standard frequency shift of an FM modulated audio signal is +/- 50 KHz, the frequency shift 2.DELTA.f=548 Hz corresponds to -45.2 dB of the standard frequency shift.
In other words, if the rotary cylinder S has an eccentric displacement 5 .mu.m, unnecessary signal of -45.2 dB is always superposed upon the signal reproduced from an FM modulated audio signal having the standard frequency shift.
Such frequency fluctuations are canceled out if the same magnetic recording/reproducing apparatus is used for both recording and reproducing, thereby posing no problem. However, if different magnetic recording/reproducing apparatuses are used, the fluctuation during recording is added to the fluctuation during reproducing, two-folding the fluctuation at the worst. Such a fluctuation is called jitter which is outputted as noises of a reproduced audio signal, thereby deteriorating the commercial value of a recording/reproducing apparatus.
One of conventional noise reduction apparatuses is disclosed, for example, in Japanese Patent Laid-open Publication No. 61-236071. The outline of this apparatus will be described with reference to a block diagram of FIG. 2 and timing charts of FIGS. 3 and 4.
An audio signal obtained through FM demodulation is inputted to an input terminal 1 and supplied to a bandpass filter (BPF) 2 having a passband between, e.g., 30 and 500 Hz. The band-passed audio signal is supplied via a sample-hold (S/H) circuit 4 to an analog-digital (A/D) converter 5. A digital data outputted from the A/D converter 5 is applied to a terminal a of a first switch SW1. The first switch SW1 has two contacts b and c to which a first random access memory (RAM) 7 and a second RAM 8 are connected respectively, so that the digital data is written in either RAM 7 or RAM 8 depending upon the switching state of SW1. RAM 7 and RAM 8 are connected to contacts e and f of a second switch SW2 so that a digital data is read from either RAM 7 or RAM 8 depending upon the switching state of SW2, and applied via a contact d to one input of a comparison gate circuit 6. Applied to the other input terminal of the comparison gate circuit 6 is the digital data outputted directly from the A/D converter 5. Outputs of the comparison gate circuit 6 are applied to a comparison circuit 13.
A synchronous pulse signal Ps, e.g., of 30 Hz, synchronous with the rotation of the rotary cylinder S is supplied to an input terminal 9 to generate a clock pulse signal CK.sub.1 of 1.2 KHz frequency-multiplied by 40 by a phase locked loop (PLL) 10 and timing counter 11. This clock pulse signal CK.sub.1 is supplied to the A/D converter 5 as its sample timing signal. The clock pulse CK.sub.1 and synchronous pulse signal Ps are supplied to a control circuit 12, with a comparison result signal (error signal) of the comparison circuit 13 being also supplied thereto. The control circuit 12 supplies a control signal X to the first RAM 7 and another control signal Y complementary to the control signal X to the second RAM 8. The control signal X changes its level alternately with the synchronous pulse signal Ps in the ordinary state, and does not change its level when an error signal is supplied from the comparison circuit 13. The control circuit 12 supplies a control signal Z to the switch SW1, and supplies via an inverter 14 a signal complementary to the control signal Z to the switch SW2. The control signal Z changes its level with the synchronous pulse signal Ps.
When the output of the control signal Z takes a high level "H", as shown in FIG. 2, the contacts a and b of the switch SW1 are connected together, whereas the contacts f and d of the switch SW2 are connected together. On the contrary, when the output of the control signal Z takes a low level "L", the contacts a and c of the switch SW1 are connected together, whereas the contacts e and d are connected together, taking the reverse state shown in FIG. 2.
While the N-th order data shown in FIG. 3(b) is outputted from the A/D converter 5 synchronously with the synchronous signal Ps shown in FIG. 3(a), the control circuit 12 outputs the control signal Z of "H" level. During this period, the control signal X of "L" level shown in FIG. 3(f) is supplied to the first RAM 7, so that the N-th data is written in RAM 7 via the switch SW1 as shown in FIG. 3(g). The control signal Y of "H" level shown in FIG. 3(h) is supplied to the second RAM 8, so that the (N-1)-th data already written is read from RAM 8 via the switch SW2. The read-out data is supplied to the one input of the comparison gate circuit 6 as described previously. During this period, the N-th data is supplied from the A/D converter 5 to the other input of the comparison gate circuit 6. These two data are supplied to the comparison circuit 13 from the comparison gate circuit 6 which operates in response to the inverted clock pulse CK(IV)1.
FIG. 4 illustrates the operation of the comparison circuit 13. It is assumed that data indicated by the solid line in FIG. 4(b) are sequentially supplied synchronously with the synchronous pulse signal Ps shown in FIG. 4(a). If the data to be compared exceeds a threshold value t indicated by broken lines in FIG. 4(b), an error signal of "L" level is supplied to the control circuit 12. Accordingly, during the period while the N-th data is outputted from the A/D converter 5, if a difference from the (N-1)-th data is equal to or smaller than the threshold value t, a signal of "H" level from the comparison circuit 13 is supplied to the control circuit 12. During this period, the (N-1)-th data is converted into a complement (1's complement) signal by a complement circuit 15 and supplied to a D/A converter 17. Namely, a digital signal processing of obtaining a signal having an inverted phase of the input signal is carried out, and the obtained signal is supplied to the D/A converter 17. Supplied to this D/A converter 17 is the clock pulse signal CK(IV).sub. 1 whose level has been inverted by an inverter 16. The D/A converter 17 converts the input data into an analog signal. This analog signal is then applied to an adder 3 via a low-pass filter (LPF) 18 for eliminating high frequency components of the analog signal. In the meantime, the audio signal applied to the input terminal 1 is delayed by a delay circuit 19 by one period of the clock pulse signal CK(IV).sub.1, and applied to the adder 3. As a result, the adder 3 removes noises from the (N-1)-th audio signal and outputs it from an output terminal 20.
As shown in FIG. 3 (a) and (b), if an error erl is detected regarding the (N+1)-th data outputted from the A/D converter 5, the comparison circuit 13 supplies a signal of "L" level to the control circuit 12. Therefore, when the (N+2)-th data is outputted from the A/D converter 5, the levels of the control signals X and Y of the control circuit 12 take the same levels as those when the (N+1)-th data was outputted from the A/D converter 5. Accordingly, the N-th data read from RAM 7 and the (N+1)-th data outputted from the A/D converter 13 are applied to the comparison circuit 13, and the N-th data is D/A converted and supplied to the adder 3.
In the above way, when excessive noise components are detected, the previous data is used thereby eliminating jitter noises.
The above-described conventional noise reduction apparatus extracts jitter noise by using BPF 2 having the passband between 30 and 500 Hz. However, audio signal components about ten times as much as jitter noises are often present within this band. With the conventional apparatus, these audio signal components are assumed as jitter noises during the reduction process of noises, resulting in a low reliability.